1. Field of the Invention
The present disclosure generally relates to the fabrication of integrated circuits, and, more particularly, to various methods for forming mask layers using a flowable carbon-containing silicon dioxide material.
2. Description of the Related Art
In modern integrated circuits, such as microprocessors, storage devices and the like, a very large number of circuit elements, especially transistors, are provided on a restricted chip area. Transistors come in a variety of shapes and forms, e.g., planar transistors, FinFET transistors, nanowire devices, etc. The transistors are typically either NMOS (NFET) or PMOS (PFET) type devices wherein the “N” and “P” designation is based upon the type of dopants used to create the source/drain regions of the devices. So-called CMOS (Complementary Metal Oxide Semiconductor) technology or products refers to integrated circuit products that are manufactured using both NMOS and PMOS transistor devices. Irrespective of the physical configuration of the transistor device, each device comprises drain and source regions and a gate electrode structure positioned above and between the source/drain regions. Upon application of an appropriate control voltage to the gate electrode, a conductive channel region forms between the drain region and the source region.
In some applications, fins for FinFET devices are formed such that the fin is vertically spaced apart from and above the substrate, with an isolation material positioned between the fin and the substrate. FIG. 1 is a perspective view of an illustrative prior art FinFET semiconductor device 100 that is formed above a semiconductor substrate 105 at an intermediate point during fabrication. In this example, the FinFET device 100 includes three illustrative fins 110, an isolation material 130 (e.g., silicon dioxide, a low-k material or an ultra-low-k material), a gate structure 115, sidewall spacers 120 (e.g., silicon nitride) and a gate cap layer 125 (e.g., silicon nitride). The fins 110 have a three-dimensional configuration: a height, a width and an axial length. The portions of the fins 110 covered by the gate structure 115 are the channel regions of the FinFET device 100, while the portions of the fins 110 positioned laterally outside of the spacers 120 are part of the source/drain regions of the device 100. Although not depicted, the portions of the fins 110 in the source/drain regions may have additional epi semiconductor material formed thereon in either a merged or unmerged condition.
Typically, fins are formed in a regular array. The critical dimensions (CD) of the fins in the array are determined by the photolithography process employed in patterning the fins. Various techniques may be employed to achieve feature sizes that are smaller than the resolution limit of current photolithography processes. Techniques known in the art include double exposure, double patterning, spacer double patterning, self-aligned double patterning and self-aligned quadruple patterning. Due to their process complexities and material limitations, such processes present many challenges with respect to dimensional control, including CD erosion and pitch walking (i.e., non-uniformities in fin pitch and periodicity across the array).
Another problem area with semiconductor device fabrication in the deep sub-micron range is the patterning of interconnect features for the devices. As the size of the individual circuit elements is significantly reduced, thereby improving, for example, the switching speed of the transistor elements, the available floor space for interconnect lines electrically connecting the individual circuit elements is also decreased. Consequently, the dimensions of these interconnect lines and the spaces between the metal lines have to be reduced to compensate for a reduced amount of available floor space and for an increased number of circuit elements provided per unit area.
The present disclosure is directed to various methods and resulting devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.